A planar type EEPROM cell structure by standard CMOS process for integration with gate array, standard cell, microprocessor and for neural chips

A planar-type EEPROM (electrically erasable programmable read-only memory) cell structure which consists of adjacently NMOS and PMOS transistors with an electrically isolated common polysilicon gate has been prepared by a standard CMOS process (no ultrathin oxide, no stacking of floating and control gates). Five to ten volt shifts of threshold and more than thousands of cycles of endurance are obtained. This EEPROM cell can be easily integrated with gate array, standard cell, microprocessor LSIs. It can store analog data and be applied to neural chips.