A CMOS signed multiplier using wave pipelining

The authors present a high-performance 8 /spl times/ 8 CMOS signed multiplier using the wave pipelining technique. The multiplier architecture is based on the modified Booth algorithm and Wallace-Tree techniques. At the transistor level, a biased CMOS gate is used to balance the path delays; it provides a means of postprocess tuning, even though it has a disadvantage in power consumption. The multiplier is implemented with MOSIS 2-/spl mu/m technology, and simulation results show a tenfold speed-up over nonpipelined operation.