Performance-driven layout through device sizing

A system for performance-driven layout of cell-based integrated circuits is presented. Initial specification of performance goals and postlayout timing analysis are used to drive module generation and physical layout tools. Communication between the physical and analysis tools allows a new buffer sizing algorithm to perform static timing analysis on the network under modification. Solutions are selected based on accurate delay data rather than estimations. This approach has the following advantages: strong control over path delays through buffer sizing, accurate calculation of path delays, including those due to routing parasitics, and low computational complexity, which allows automatic, full-chip optimization.