HDL and integrating system-level simulation technologies

System level design is a critical component of any electronics product development project. However, HDL based ASIC design has remained a distinctive and separate function within projects. With the advent of deep submicron technology, large systems and subsystems can now be placed on a single chip. This requires a closer interaction between system level design and ASIC development. The paper describes an effective methodology and technology support for integrating system level simulation techniques with HDL based simulation to provide a smooth transition between each level. We start by examining an integrated verification methodology and the use models for utilizing mixed dataflow and HDL models. We then discuss combining a model of interaction derived from the work done on the Ptolemy project with a standards based implementation approach using the Open Model Forum (OMF) standard. Finally, an example is used to highlight the effectiveness of this approach.