Evaluating the throughput of cluster tools using event-graph simulations

Semiconductor wafer manufacturing equipment, such as cluster-tools and flexible lithography tracks, often contains several process modules combined with one or more wafer handlers. Equipment designers and owners are interested in simulating the throughput of this complex equipment. As an alternative to traditional discrete-event simulations, we have used the event-graph and resident-entity approaches to build a flexible simulator. The simulator was written in C++ (an object-oriented extension to C) and has proven to be easily extendible. Compared with simulators using more traditional approaches and implemented in specialized simulation languages, it runs extremely fast. Execution times are orders of magnitude less, even on low-end hardware with limited memory. Using a built-in, full-factorial experiment generator, we have been able to quickly evaluate many possible equipment configurations. The event-graph approach involves examining the key events in a process, their effect on the state of the system, and their relationship with other events. The events in the model are associated with resident entities (the wafer handlers and process modules) not the transient entities (individual wafers). This enables faster execution, especially in systems with large batch sizes and a large number of wafers. We used the inheritance features of C++ to ease the addition of new types of process models and wafer handlers.