Recent progress in development of SOI pixel detectors

We are developing monolithic pixel detectors with a 0.2 um CMOS, fully-depleted silicon-on-insulator (SOI) technology. The substrate is high-resistivity silicon and works as a radiation sensor having p-n junctions. The SOI layer is a 40 nm thick silicon, where readout electronics is implemented. There is a buried oxide (BOX) layer between these silicon layers. There is no mechanical bonding in the SOI pixel detector between sensor and front-end electronics, so fine segmentation and lower mass are expected compared with hybrid detectors. These kinds of pixel detectors are also useful in various research fields, such as high-energy physics, X-ray material analysis, astrophysics and medical sciences. We have already done several Multi Project Wafer (MPW) runs by gathering many pixel designs into a photo mask set. In this document, ongoing R&Ds are described. One of recent progress is the implementation of the Buried P-Well (BPW) process. The effectiveness of the BPW was evaluated by including the pixel detector design. The other steps to proceed this R&D project are also described.