Charging characteristics of high dose source implants of DMOS devices

We have studied the charging characteristics of vertical and trench power double-diffused MOS (DMOS) devices during the high current source implants. Both n-channel and p-channel DMOS devices implants by dopant species of As, P or B have been investigated. When unfavorable process conditions, such as high beam current density, the malfunction of the secondary suppression high voltage system and the lack of a flood gun, are inadvertently created, the gate oxide integrity is greatly affected causing excessive gate-to-source (I/sub gsx/) leakage current of some of the DMOS devices. In terms of the implant dopant species, As has the most charging effects and B has the least. We believe that the differences of sputtering coefficients of As and B may have played an important role of determining the severity of the wafer charging by the difference of generating secondary electrons. By deprocessing the damaged wafers, the locations of gate oxide damages have been found mainly at the perimetric region of the oxide. This observation is consistent with the result that the die size has the biggest impact on the gate oxide survival rate, while the oxide thickness has much less impact on the yield under the charging conditions we have generated. Another surprising result is that the trench DMOS devices are more reliant against charging effects that the vertical DMOS devices. This result indicates the importance of minimizing the process-induced damages (e.g. etch or ion implantation) of the exposed regions of the gate oxides. Consequently, it is advisable to employ a polysilicon re-oxidation or an oxidation during S/D anneal to ameliorate gate edge damage produced by the poly etch or the source/drain implant.