A 3 V/650 MHz, 5 V/910 MHz CMOS dual modulus prescaler for low power, low input-amplitude applications

A low power dual modulus prescaler for frequency synthesisers has been designed in a standard 1.2 /spl mu/m digital CMOS process using enhancement source coupled logic (ESCL). Being a differential low amplitude current mode logic, ESCL has two interesting characteristics for this design: the low noise performance, that allows this circuit to be on the same chip with sensitive analog circuitry, and the ability to run with a 300 mV sinusoidal signal as generated from an LC oscillator without the need of a clock amplifier. The maximum operating frequency for the prescaler is 910 MHz at 5 V and 650 MHz at 3 V. At 195 MHz and 3 V, the current consumption is as low as 289 /spl mu/A.