Use of statecharts-related description to achieve testable design of control subsystems

Control-dominated architectures are efficiently described by means of graphical representations based on statecharts. Statecharts descriptions can be automatically translated into HDL representations (VHDL or Verilog) which are directly synthesized into gate-level netlists. This paper describes a set of rules which transform, if possible, a statecharts description into a simpler representation based on hierarchically interconnected FSMs (HFSM). The comparison of the HFSM description with the gate-level synthesized net-list allows to efficiently perform redundancies removal and test pattern generation. Thus, by applying the proposed testing strategy, fully testable implementations can be obtained even for such devices which cannot be satisfactorily analyzed at the gate level only.