Multichannel SDRAM controller design for H.264/AVC video decoder

Embedded consumer electronics like video processing systems require large storage capacity and high bandwidth memory access. Also, those systems are built from heterogeneous processing units, designed specifically to perform dedicated tasks in order to maximize the processing power. A single off-chip memory is shared between the processing units to reduce power and save costs. The external memory access is the system bottleneck when decoding high definition video sequences in real time. This paper presents the design and validation of a multichannel DDR2 SDRAM controller design for a H.264/AVC video decoder. A four-level memory hierarchy was designed to manage the decoded video in macroblock granularity with low latency. The proposed controller is able to manage memory access in decoding 1080p H.264 video sequences. This architecture was validated and prototyped using a Xilinx Virtex-5 FPGA board.