A novel nanoscale staggered 6T SRAM cell layout to mitigate multiple nodes charge collection effect

As CMOS device size shrinks, the spacing of the sensitive devices in one memory bit is decreased. But the width of the single-event charge track does not shrink, so one particle probably affects several sensitive devices in one memory bit. In this paper, a novel nanoscale 6T SRAM cell layout is proposed to mitigate this effect. This method separates one cell into two symmetrical parts and one layout forms two cells (A and B) in staggered arrangement: 0.5A 0.5B 0.5A 0.5B. So two sensitive transistors in one 6T cell are effectively divided in space and prevent the single-event upset (SEU) caused by multiple nodes charge collection (MNCC) effect, especially for these low energy, large incidence particles. Through HSPICE simulation, this method enhances critical charge of MNCC 37% and point out critical charge can be diminished significantly by MNCC. The area overhead of this novel layout is small and can be used in any kind of symmetric storage cells.