Embedded compiler optimization for communication applications

Nowadays embedded processor manufactures extend their architectures to include blocks that perform digital signal processing functions. One of these blocks is address generation units (AGUs) which have been typically provided in digital signal processors (DSPs). The AGUs play an important role in code generation for communication applications where a large number of memory accesses are made. In this paper we propose an effective address code generation approach for communication applications to minimize the number of instructions that calculate memory address. Our work tightly couples offset assignment (OA) with modify register optimization (MRO) in an iterative framework. Experimental results with benchmarks show average improvements of 29% in the addressing cost over previous approaches.