Time-predictable multicore cache architectures

To enable multi-core computing for real-time systems, the time-predictability of multi-core caches must be improved. This paper explores several time-predictable instruction cache architectures to guarantee time predictability of instruction accesses by real-time threads without significantly impacting their performance (i.e., throughput). We propose a prioritized cache that gives priority to instructions of real-time threads while allowing all the threads to share the aggregate cache space. Also, we study a prioritized-partitioned cache to provide decent performance to non-real-time threads without compromising the time predictability of real-time threads. Our experiments indicate that the proposed time-predictable instruction cache architectures can be used for different real-time applications with various instruction access behaviors for balancing time predictability and performance.