A new approach for TCP/IP offload engine implementation in embedded systems

TCP/IP offload engine (TOE) is an essential technology to increase throughput of network connection. In this paper we present a novel approach for TOE implementation in embedded system with very stringent requirements on area and power. Our approach is based on two design optimizations. The first one deals with architectural enhancement for reducing the size of memory buffers in TOE hardware. The second one optimizes the TCP/IP data flow in order to speculatively process the TCP/IP packet headers in parallel to DMA data transfers. Experiments show that the approach is very effective. A prototype design of TOE receiver operating at a very low (25 MHz) frequency can achieve 13.1 Mbs throughput while requiring only 57.5 K 2-input NAND logic gates for control logic.