Design and FPGA implementation of radix-10 combined division/square root algorithm with limited precision primitives

A combined decimal division/square root scheme using limited-precision multipliers, adders, and table-lookups is presented. The combined algorithm, except in the initialization steps, uses a slightly modified digit-recurrence algorithm for division with limited-precision primitives. We describe the proposed combined division/square root algorithm, a design, and its FPGA implementation on a Xilinx Virtex-6 FPGA. We present the cost and delay characteristics for precisions of 7 (single-precision), 8, 14 (double-precision), 16, 24, and 32 decimal digits. The costs range from 1384 to 4066 LUTs with maximum clock frequencies around 68 MHz, and latencies ranging from 102 to 485 ns (with unoptimized routing delays). The proposed scheme uses short (2 to 4 digit-wide) operators which leads to compact modules, and may have an advantage at the layout level as well as in power optimization. The proposed approach is general and can be adapted to other higher radix combined division/square root implementations.