An improved configurable 2-D linear feedback shift register for embedded core built-in self-test

This paper presents an optimization scheme for the synthesis of built-in self-test circuitry for embedded cores. This scheme is based on a two dimensional linear feedback shift registers that make use of XOR and XNOR gates. The proposed scheme results in configuration networks with up to 33% reduction in XOR gate inputs and up to 25% reduction in transistor count as compared to prior work in 2-D linear feedback shift registers.