Hybrid simulation using functional single-electron transistor models

Recent advances in the fabrication of single-electron devices (SEDs) and the forthcoming combination of them with nanometric CMOS transistors to form hybrid circuits forcibly put in scene the need of solid and robust simulation methodologies for these classes of circuits. In this paper a verification path that incorporates functional models for the SEDs in order to achieve simulation of bybrid circuits is expound. Several examples illustrate the application of the verification methodology.