Configurable controller for rapid development of satellite sensor systems

In an effort to improve instrument resource usage and key development metrics, we have developed a field programmable gate array (FPGA) based sampling controller to be used as the core timing controller for the satellite borne sensor systems developed and produced at the University of Texas at Dallas. The newly developed sampling controller core produces the required function triggering patterns and addressing patterns by decoding a continuously running counter output to generate function enable and address selection signals. The system architecture, implementation approach, and results of demonstration design synthesis are described. We present a software design tool that facilitates rapid system development and verification, while providing the basis of the system documentation as part of the design flow. The high level of system modularity and parameterization helps to maximize module reuse from one design to the next, and reduce design effort for each particular design. Compared to previous approaches, the new approach is a significant improvement in key programmatic areas of interest including system documentation, overall system simplicity, and design cycle time.