Power gating techniques on Platform Controller Hub

Energy efficiency has long been a first-order goal for mobile devices such as cell phones to extend battery life. In the last decade, effective energy use has also become a focus for larger computing devices for several reasons; namely expansion of mobile computing and data centers. Customers require maximum battery life from notebooks, netbooks, and tablets. Achieving optimal battery performance requires careful management of energy consumption. This paper describes the power gating techniques which has achieved ∼1000mW of effective power savings on Platform Controller Hub (PCH) and is proven to be a good strategy for preserving mobile computing power and extension of battery life span. However, to make power savings possible without performance trade-off, many design considerations combining architecture, floorplanning, innovative hardware design and software configurations are required. This paper presents the power gating strategies starting from early design planning to post silicon validation correlation methodology considering: 1) silicon floorplan partitioning into multiple power domains 2) stages of PFET switches assignment 3) The trade-off between a wake-up overhead and leakage savings design 4) the complete definition of power gate/ungate power sequence from partition level to system level 5) PDN noise analysis and leveraging of “zero-cost” noise mitigation techniques to address the various possible worst case power noise droop events cause by power gate/ungate activities. These power gating strategies are consider successful, when not only the desired power target is achieved; but a smooth transition of power state from sleep mode to full power mode and vice versa, is achieved without system hang or performance corruption. The paper is concluded with post silicon validation results correlated to selected individual power partition's gate/ungate activity; which is controlled by a specially customized test script to examine the power fet's gating/ungating functionality v.s. design expectation.