PXIe Based High-Speed Transmission System Design and Implementation

PXIe protocol is a novel high-speed transmission bus protocol in industry. PXIe not only offers high performance up to 500MB/s bandwidth (4 lines), but also is completely compatible with PCI Express protocol. However, the current implementation in FPGA can not make full use of its advantages. The paper describes a direct memory access system to improve the real bandwidth of PXIe bus. For direct memory access can operate either as a master or a slave device for PXIe bus, two combined modules are designed to deal with two conditions respectively. Furthermore, a buffer sub-system utilizing DDR2 SDRAM is proposed to satisfy the demands of both high data throughput rate and large capacity in the high-speed environment. Measured experimental results confirm that the direct memory access system increases the bandwidth of original data transfer rate from 100MB/s to 500MB/s with very low bit error rate.