Novel High Speed MCML 8-Bit by 8-Bit Multiplier

Increasing demand for high-speed applications in communication has shaped the need for highly integrated, high speed multiplier. A logic style that is becoming increasingly popular is MOS Current Mode Logic (MCML) due to its distinct advantages over conventional CMOS logic for high-speed applications. In this paper an 8-bit by 8-bit pipelined tree type multiplier designed using MCML, is presented. The architecture is proposed and the operation is explained for high-speed applications supported by simulation results. An optimization method for designing the universal MCML gate for high-speed application is discussed. The optimum throughput for the pipelined tree type multiplier is obtained at 1.31GHz. All simulations are performed on a 0.6μm standard CMOS double metal double poly process, using Cadence Design Tools.