Performance analysis of convolutional interleaver on TMS320C6711 Digital Signal Processing Kit

The work presented in this paper is aimed at designing an optimized convolutional interleaver for realtime application using Digital Signal Processor. Interleaving is a simple and effective means to improve the performance of an error correction scheme on a bursty channel. Convolutional interleaver is considered as one of the best option for researchers besides of block and helical interleaver. In non-real-time application, there have been many examples or simulations of convolutional interleaver, written in C language but the problem is, most of them requires many loops to execute and hence, cause timing problem. Thus, this is not suitable for real-time application. Therefore, this research proposed the solutions to the latency problem by satisfying several requirements simultaneously: 1) using DSP-BIOS Scheduling module such as SWI and PIPE to increase performance and make sure sample data are in packed, 2) removing loop algorithm in interleaver function with look-up table method and 3) using compiler optimization that was provided in Code Composer Studio. Finally, the optimized codes are implemented on TMS320C6711 DSK and the codes performances are collected through DSP/BIOS analysis modules. From the implementation results, it shows that the proposed algorithm promising a good performance compare to the original algorithm in terms of speed and memory size.