A 100 MS/sec, 8th-order quadrature Sigma-Delta ADC for complex-IF signal digitization in a wideband-IF sampling receiver

The paper presents a 100 MS/sec fully differential quadrature Sigma-Delta ADC, implemented on a standard 0.35 μm CMOS process for application in wideband-IF sampling receivers. The circuit performs complex-IF signal digitization as well as IF-to-Baseband frequency conversion of multistandard communication channels. It demonstrates the feasibility of digitizing quadrature IF-signals with sampling rates in the range of 100 MHz and an IF set to 3/4 of the sampling frequency. The ADC architecture is based on a quadrature IF sampling and mixing topology followed by I/Q lowpass Sigma-Delta modulators performing spectrally shaped signal quantization at baseband. The prototyped ASIC is aimed for application in multi-mode GSM/WCDMA mobile terminals with channel bandwidths of 200 kHz and 3.84 MHz, respectively. Simulation results for both, UTRA-FDD and GSM are given.