An auto-zero sample-and-hold circuit in 0.8 μm CMOS

This work describes the silicon implementation of a new sample-and-hold circuit topology. The main feature of the circuit is its auto-zero capability. The auto-zero corrects the offset voltage generated by the transistor mismatch in the differential pair and the charge injected by the NMOS switches in the sampling capacitor. The circuit was implemented in 0.8 μm CMOS process from AMS. The results, initially obtained from simulations, were compared to real laboratory measurements. The comparison indicates that the measurements and the simulated results have a very close correspondence. The circuit is capable of reducing the total sample-and-hold output error to just 0.14% at a sampling rate of 250 KHz.