A high performance embedded SRAM compiler

This paper describes a high performance embedded SRAM compiler based on 0.18 μm standard CMOS process. It can generate various single-port SRAM configurations with a maximal capacity 1 M bits according to the parameters provided by users. These SRAMs feature synchronism, low power and high speed. The compiler structure and circuit design techniques are thoroughly elaborated in this paper. The self-timing strategy by replica cells and a pulsed-clock control module are applied for high speed and low power purpose.