Study on high performance bus interface of RISC microprocessor

The performance gap caused by higher clock rate of processor and lower of DRAM is severe, and the memory system becomes one of the primary bottlenecks. Further, within the memory system, the memory bus accounts for a substantial portion of the primary memory's overhead. Some approaches are studied in this paper to improve the performance of the microprocessor bus interface, including out-of-order, pipelined and split-bus transaction, load/store buffer model and the design of asynchronous interface. These methods are used in the design of ARS03 microprocessor that we developed to implement an efficient processor bus interface, to facilitate access to main memory and other bus subsystems. The simulation results of real programs show that the penalties of long memory latencies are mitigated. The execution cycles are reduced at a rate 9.1% to 36.7%.