Virtual core based synthesis of SoC architectures

The reuse of high-level design intellectual properties is indispensable to reduce SoC design time. It has been difficult for SoC designers to design and compare two or more SoC architectures in a given product design time. In this paper, we present a synthesis methodology of SoC architectures using Virtual Cores (VCores) to perform architectural explorations in a short period. The proposed synthesis methodology generates an initial architecture, which consists of a CPU, buses, I/Os, etc., and makes tradeoffs between hardware and software on mapped software VCores and hardware VCores models. The authors show the usefulness of the proposed method from the results of an architecture level design experiment.