A reconfigurable architecture of a high performance 32-bit MAC unit for embedded DSP

This paper describes a reconfigurable architecture of a high-performance pipelined 32-bit multiply-accumulate unit (MAC), which is designed for a powerful embedded digital signal processor (DSP). The MAC unit we design can carry out two 16-bit multiplications in one clock cycle. The 32×16, 32×32, 32×16+80 and 32×32+80 operations can be implemented in two clock cycles. These characteristics allow the DSP being applied efficiently in different situations. A 2 stage pipeline is designed for this MAC unit to reach high throughputs. This MAC is synthesizable and has already been used in an embedded DSP core.