Physical implementation and test of energy recovery circuit

This paper presents a new structure of energy recovery logic named improved energy recovery logic (IERL) and discusses the physical implementation issues. A feasible test schemes for function verification and power measurement of energy recovery logic circuit is proposed and put in practice. The test results verified the proper function of IERL 2-bit full adder (FA) circuit and the low power performance. When the power clock is set at 2MHz, the average power consumption of IERL 2-bit FA is 66% of its CMOS counterpart.