New design of RF interface circuits for PICC complying with ISO/IEC14443-2 type B

This paper demonstrates a new set of RF circuits design proposal for PICC complying with ISO/IEC 14443-2 Type B, expatiates on the topology of typical modules and addresses its advantage over former design. The simulation data by Hspice, with the corresponding test of this chip is also given in the following thesis. The design has been implemented upon 0.8 μm CMOS technology successfully. The packaged chip can operate at 13.56MHz with data rate of 106 kbps, hence its feasibility is verified.