Trends in low-power RAM circuit technologies

Trends in low-power RAM circuit technologies are reviewed. The following provide major contribution to power reduction: lowering operating voltage by lowering the external supply voltage, half-V/sub DD/ data-line precharging and on-chip voltage down converting; reducing charging capacitance through partial activation of multi-divided array, and CMOS NAND decoder; reducing DC current through partial activation of multi-divided word line and pulsed operations of periphery using address transition detection. These contributions have made possible a DRAM active power reduction of as much as 2 to 3 orders of magnitude over the last decade. Moreover, MOS transistor subthreshold current reduction circuits such as source-gate backbiasing scheme, which are essential in an ultra-low voltage era, might reduce an active current of a 1-V 16Gb DRAM from 1.2 A down to 22 mA.