Design considerations for low-power, high-speed CMOS analog/digital converters

This paper reviews architectural and circuit design considerations for realization of low power dissipation in high-speed CMOS A/D converters. Basic limitations on achievable power dissipation in MOS samplers and quantizers is first discussed. Then a number of practical design aspects are illustrated with discussion of a 10-bit, 20-Msample/s pipeline A/D converter implemented in 1.2-/spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation on a 3.3 V power supply.