System and architecture optimizations for low power MPEG-1 video decoding

Providing MPEG-1 video decoding capability in a low power device requires optimizations at the circuit, architecture, and system levels. In this paper several architecture and system level optimizations are described that allow the decoding of unmodified MPEG-1 bitstreams at CIF resolutions with significantly lower power. These techniques can be used together with a reduced supply voltage to provide MPEG-1 video capability in a battery-powered multimedia device.