CMOS current steering logic for low-power mixed-signal systems

An analog-friendly logic family - Current Steering Logic (CSL) has been developed for high-speed, high-precision, low-power CMOS mixed-signal ICs. The constant current characteristic of CSL provides a 100X noise reduction compared to static logic. The speed of CSL can be controlled over a wide range since it is determined by the DC bias current. A 39-stage CSL ring oscillator in standard 1.2 /spl mu/m CMOS with V/sub dd/=1.1 V and I/sub bias/=12.5 /spl mu/A exhibited 1.1 ns delay and 15 fJ PDP; another design in standard 0.8 /spl mu/m CMOS with V/sub dd/=1.0 V and I/sub bias/=0.3 /spl mu/A showed 28 ns delay and 8 fJ PDP.