A fully integrated design methodology for 100 K-gate CMOS custom LSIs with TAB packaging

A fully integrated design methodology based on a 1.0-μm CMOS standard cell technology with tape automated bonding (TAB) packaging has been developed to design and fabricate maximum 100 K-gate custom LSIs. The methodology has been successfully applied to the design of an I/O control processor. The processor was fabricated and housed in a 321-pin PGA (pin-grid-array)-type TAB package