CMOS high speed digital datastrobe processor

A 1.3-μm CMOS high-speed digital datastrobe processor (DDP) is described. This device uses a high-speed (15 MS/s) 7-bit half-flash analog-to-digital converter, a digital wave equalizer, and a digital phase-locked loop. The DDP has 27 K transistors in a 4.75×4.90 mm ² chip size and consumes 100 mW