0.8 μm 1.4 MTr. CMOS SOG based on column macro-cell

Column macro-cell architecture has been verified to be advantageous for increasing silicon utilization in experimental circuit layouts. As an application, a 64-b multiplier with 32-kb RAM and 65-kb ROM using a 1.4-M transistor sea of gates (SOG) has been developed, using 0.8-μm two-layer-metal CMOS. Gate density of 1.5 kg/mm² and bit densities of 1.9 kb/mm² for RAM and 6.3/mm² for ROM have been achieved