On the design of quaternary comparators

Quaternary logic requires a dedicated comparator circuit besides the usual add/sub unit which may not be optimal due to several reasons. In this paper, we have thoroughly discussed various alternative expressions for equality operator which serves as the basis for quaternary comparator. Then we have derived the necessary equations for single qudit comparator and extended it to serial multi qudit comparator. We have also shown the equations and design of single stage parallel comparator where restriction of fan-in is sacrificed for constant speed. We have ended our discussion with the design of a logarithmic stage parallel comparator which can compute the comparator output within log
2
(n) time delay for n qudits.