HLS approach in designing FPGA-based custom coprocessor for image preprocessing

Control the data flow between device interfaces, processing blocks and memories in a vision system is complex in hardware implementation. In the research, high-level synthesis tool is used to design, implement and test the vision system within the context of required control, synchronization, and parameterization on a processor based platform. In addition, both HLS tools and HDL were used for the development of the processing cores, and the performance of the two versions were analyzed and compared. The operational structures of benchmarked vision core consist of custom vision coprocessor with efficient memory and bus interfaces. The performance properties such as accuracy, throughput and efficiency are measured and presented. Xilinx XC5VLX110T FPGA, has been used for prototype the hardware platforms. According to results, without any complex optimizations, pipeline length and resource utilization was achieved compared with the HDL counterpart. Our image pre-processing architecture which was implemented using HLL is faster than the optimized software implementation on an Intel Core 2 Duo GPU. The development time using AccelDSP was roughly five times shorter than using Verilog. Therefore, the availability of competent high-level synthesis tools will significantly reduce costs and design constraints in embedded image-processing implementations on FPGA.