A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

We show that FinFET, a leading transistor architecture candidate of choice for high performance CPU applications, can also be extended for general purpose SoC applications by proper device optimization. We demonstrate superior, best-in-its-class performance to our knowledge, as well as multi-Vt flexibility for low-operating power (LOP) applications. By high-k/metal-gate (HK/MG) and process flow optimizations, significant drive current (I
_ON
) improvement and leakage current (I
_OFF
) reduction have been achieved through equivalent oxide thickness (EOT) scaling and carrier mobility improvement. N-FinFET and P-FinFET achieve, when normalized to Weff (Weff=2xHf+Wf), I
_ON
of 1325 μA/μm and 1000 μA/μm at 1 nA/μm leakage current under V
_DD
of 1 V, and 960 uA/um and 690 uA/um at 1 nA/um under Vdd of 0.8V, respectively. This FinFET transistor module is promising for a 32/28nm SoC technology.