Design for reliability in via middle and via last 3-D chipstacks incorporating TSVs

Two test chips have been designed to determine the performance, yield and reliability of 3D chipstacks using Through Silicon Vias (TSVs). One of the chips uses via-middle technology while the other uses via-last technology. Both chips are fabricated in a commercial foundry using a 65 nm CMOS process. Both chips contain test structures designed to measure performance of transistors and other active devices, the resistance and electromigration performance of TSVs and microbumps, thermal performance, corrosion related to moisture ingress. This paper will focus on the reliability features of the chips, excluding the active devices.