Achievement and future challenges in 3D researches

The slides present the following: 3D technology; insulation; die-wafer bonding; thin wafer handling; thermal enhancement; alternative technologies to TSV: face-to-face bonding, wireless I/O, epifilm bonding, chip-size SiP, non-3D wafer level package; 3D integration; via formation- base line, laser drilling, critical etching control for backside via; insulation material- polymers; parasitic capacitance; CVD oxide; thermal oxide; Cu TSV filling; copper bulging; gold stud bump; bottom-up plating; low-cost TSV filling electroless Ni plating; thin wafer handling- laser debonding; through glass via formation; through silicon interposer; silicon interposer with air gap TSV; silicon interposer for 3D-optochip; TSV-based transmission lines; wide IO memory; fan-out WLP and integration; wafer-level packaging in the future; and gap analysis and summary.