An explicit model for delay and rise time for distributed RC on-chip VLSI interconnect

In this paper, simple explicit delay and rise time expressions for uniformly distributed RC on-chip interconnect line are derived based on Elmore's approximations. Here, an n-cell RC ladder network with capacitive load is used. Transfer function for the n-cell RC ladder network is obtained by using the transmission line parameter matrix for each cell. In order to deduce the transfer function, the transmission line is modeled by a lumped parameter network. From this transfer function, explicit delay and rise time expressions are derived by using Elmore's definitions. The calculated delay and rise times by our proposed closed form expressions are compared with the results obtained by SPICE simulation for n = 2, 3, 4, 5, 6, 7 cell ladder networks with capacitive load.