HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC

In this paper we present an efficient heuristic to significantly enhance yield/area of die in technologies where the inherent yield is low. Our technique makes use of a judicious use of redundancy and switching circuitry. Though our presentation is focused on pipeline (linear) structures, our techniques can be extended to apply to more general structures. The time complexity of our procedure is O(n³) for an n-stage pipeline.