A simple CMOS delay model for wide applications

In this paper, we propose a delay model of CMOS gates for wide application. After introducing a delay model for the CMOS inverter, we develop it for other CMOS gates. In this process, we first remodel the MOSFET and the input signal effectively, and then, we model the MOSFETs in the inverter as a resistor or a current source according to both the input voltage and the output voltage of the inverter such that, when the MOSFET is in the saturation mode, it is modeled as a current source and when it is in the nonsaturation mode, it is modeled as a resistor. The delay model for the CMOS inverter is simply converted for other CMOS gates by minor manipulation. Our model has an accuracy of less than 5% error rate from the SPICE simulation results for the fifteen cascaded CMOS gates of inverter, NAND and NOR.