Design and implementation of an efficient montgomery modular multiplier with a new linear systolic array

To resolve the latency problem of implementing Montgomery modular multiplication algorithm using the linear systolic array, this paper proposes the improved Montgomery algorithm, and improves the systolic array by combining the long carry save adder (CSA) structure. This paper also proposes a series of methods to optimize the critical path and a non-waiting modular multiplication strategy which can allow the exponentiator to ignore the output delay of the multiplier. At last, the new modular multiplier can provide a much higher calculation speed, and also can avoid the signal broadcasting and amplification problem of the long CSA structure. The verification prototype is built on the FPGA. The time for 1024-bit modular multiplication merely needs 4.75µs under clock frequency of 243.9 MHz.