Implementation of 20Gbit/s area-optimization DQPSK precoder employing FPGA

In this paper, a new model based on an ameliorated Brent Kung (BK) parallel prefix network (PPN) algorithm was proposed and realized in Virtex V FPGA. In the implementation, compute complexity (area) optimization was achieved. 770 slice registers was utilized and which saved 60% logic resources to the before algorithm.