High-Speed Error-Correction for Leading Zero/One Anticipator

The algorithm and its implementation of a leading zero anticipators (LZA) are very vital for the performance of a high-speed floating-point adder in current state of art microprocessor design. However, in predicting "shift amount" by a conventional LZA design, there may be one-bit error, which is mentioned as the possible error in the result. This paper compares the conventional LZA designs and presents a novel parallel error-detection algorithm for modifying the result of the LZA before it is sent off to improve the performance of the LZA. The novel error-detection algorithm does not depend on any carry-in signals of the adder. Therefore, it makes the error-correction to be parallel with the mantissas addition and increases the speed of the LZA to generate correct results significantly.