Video player parallelization and optimization for embedded asymmetric dual-core architecture

This paper addresses the implementation of a video player on an embedded asymmetric, dual-core architecture with the two cores having significantly different performances. The paper proposes a new parallelization approach that effectively handles the issues of load balancing and inter-core communication. Load balancing is based upon a coarse-grained strategy at the function level where the two cores are decoupled such that each core runs without being blocked waiting for the other. Inter-core communication is implemented through shared memory, and client stub and server skeleton functions for every remote procedure call. Optimization techniques are proposed to address the issues of memory contention between the two cores, inefficient utilization of cache memory, impact of branching instructions, intensive mathematical and data exchange functions, inefficient array access parallelization, and the dynamic memory allocation and re-allocation. The video player is implemented on Texas Instruments's DM6446 digital media evaluation module with ARM and DSP cores. It is demonstrated that with the proposed parallelization and optimization, the player is capable of playing smoothly H.264 Baseline profile and Xvid video files with 640×480 resolutions at 25 frames per second.