Application of the singular perturbation approach to an all-digital chip timing recovery loop for CDMA systems

Migration toward full-digital implementation of modems is currently one of the main trends in transmission systems design. We analyze the performance of a noncoherent all-digital delay lock loop (DDLL) suited for chip timing synchronization in band-limited direct sequence spread spectrum systems. Analytical expressions for the RMS jitter and the MTLL are presented and confirmed by a time domain computer simulation. Defining the threshold operating level for the loop as a function of the minimal MTLL the receiver can tolerate allows us to analytically calculate it and project it to a minimal allowable RMS jitter value for the loop.